1. Field of the Invention
The invention relates to a timer apparatus which is built in, for example, a microcomputer in order to control the operation of the microcomputer and, more particularly, to a timer apparatus constructed by a plurality of timers.
2. Related Background Art
There is a case where a microcomputer uses a timer apparatus comprising a plurality of timers in order to control a plurality of operating times.
Each timer of the timer apparatus has a counter and a register provided in correspondence to the counter. An operation command showing the start or stop of the operation of the counter is written into the register of each timer. The operation command to the counter is written into the register, so that the operation of the counter is controlled. The operation control of the counter results in the operation control of the timer.
A different address for each timer is previously allocated to each timer provided with the register. Address information about the address allocated to the timer including the register corresponding to the counter is given to the operation command to the counter.
The operation command to each counter is sequentially written into the register of the timer to which the address corresponding to the address information has been allocated on the basis of the address information synchronously with a clock as a reference signal of the operation of the microcomputer, so that the operation of each timer is controlled.
As mentioned above, in the conventional timer apparatus, since the addresses which are allocated to the operation commands to the counters are mutually different for every timer, the operation command to each counter is sequentially written into the register synchronously with the clock.
If the operation commands to the counters can be simultaneously written into the registers, the timers can be simultaneously made operative. In the conventional timer apparatus, however, since an address is allocated to every timer and the address information of each timer is allocated to the operation command to the counter of each timer as mentioned above, a difference occurs among the times when the operation command to the counter of each timer is written into each register. Consequently, the operation commands to the counters of the timers cannot be simultaneously written into the registers.
In the conventional timer apparatus, therefore, even when the user wants to simultaneously control the operations of a plurality of timers, a deviation corresponding to at least a period of the clock occurs in the start timing of the operation control of each timer.
Because of the above reason, in the conventional timer apparatus, the operations of a plurality of timers cannot be simultaneously controlled, for example, without adjusting the operation of the counter of each timer in a software manner. There is, consequently, a problem such that it is troublesome to simultaneously control the operations of a plurality of timers.
It is, therefore, an object of the invention to provide a timer apparatus which can simultaneously control the operations of a plurality of timers without adjusting the operation of a counter of each timer in a software manner.
According to an aspect of the invention, the above object is accomplished by a timer apparatus comprising: a plurality of counters; a register, provided in correspondence to each of the counters, for writing an operation command to each of the counters; and a distribution writing circuit for simultaneously writing each of said operation commands at bit positions corresponding to said counters of a bit train into each of said registers corresponding to each of said counters in order to control an operation of each of said counters when receiving said bit train which consists of a plurality of continuous bits to which one address information has been added and in which each of said bits indicates the operation command to said counter corresponding to each of the bit position.
In the timer apparatus according to the invention, each bit of the bit train consisting of a plurality of continuous bits added with one address indicates the operation command to the counter corresponding to each bit position. When the bit train is received, the distribution writing circuit simultaneously writes each bit of the bit train, namely, the operation commands to the counters into the registers corresponding to the counters. Thus, the operation control of each counter, namely, the operation control of each timer is simultaneously executed.
In the timer apparatus according to the invention, since the same address information is allocated to the operation command to each counter as mentioned above, the operation command to each counter is simultaneously written into each register synchronously with the clock. Thus, the start timings of the operation control to the counters, namely, the start or stop timings for the operations of the counters can be made coincide.
In the timer apparatus according to the invention, therefore, the operations of a plurality of timers can be simultaneously controlled without adjusting the operation of the counter of each timer in a software manner.
According to the timer apparatus of the invention, therefore, the operations of a plurality of timers can be relatively easily simultaneously controlled.
Further, there is provided a decoder to which an address corresponding to the address information is allocated and which transmits a decoding signal to the distribution writing circuit so as to give a write permission to the register to the distribution writing circuit when the address information corresponding to the address is received.
The register can be constructed by a flip-flop for, when a predetermined input signal is received at one of input terminals, outputting an input signal which is inputted to the other input terminal to the counter.
A bit selecting circuit, provided in correspondence to each of the counters, for outputting the bit signal to the other input terminal of the counter when the bit corresponding to the counter of the bit train is received can be also provided for the distribution writing circuit.
Further, a writing circuit, provided for each counter, for writing the bit outputted from the bit selecting circuit into the register of the counter corresponding to the bit can be also provided for the distribution writing circuit.
Each of the writing circuits simultaneously outputs an operation signal to each register so as to enable the bit which is outputted from the bit selecting circuit to be simultaneously written into each register.
The distribution writing circuit can be constructed by: a decoder to which an address corresponding to the address information is allocated and which transmits a decoding signal to give a write permission to the register to each register when the address information corresponding to the address is received; and a data bus comprising data lines which are provided in correspondence to the respective bits of the bit train and are used to transmit the bit signal of the bit position of the bit train corresponding to each counter to each corresponding counter, so that the command is written into each register by a synchronous input of the decoding signal from the decoder and the bit signal from the data line.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.